FPGA High Level Synthesis: A Survey and Implementation on Operation Scheduling Algorithms

Research background and motivation

High-level synthesis (HLS) mainly consists of three parts, inclusive of allocation, scheduling, and binding. Among them, scheduling is the most critical part of HLS. As a consequence, I decided to survey the recent development of scheduling algorithms. Nonetheless, since there are many design scenarios in the HLS, which will lead to different specialized algorithms, I will focus on the scheduling algorithm for general design in order to narrow down the topic. Then, I will also perform the implementation and experiments on the algorithms to compare the effectiveness of the recent general scheduling algorithm.

Comparison of existing scheduling algorithms

Simulation benchmark

Performance